1. Field of the Invention
The present invention relates to a processor module for a multiprocessor system and a task allocation thereof, and more particularly to a multiprocessing system having a plurality of modules.
2. Description of Related Art
In order to improve a processing speed of a microprocessor unit MPU), a multiprocessor system including a plurality of MPUs is employed. In this multiprocessor system, parallel processing is performed using a plurality of MPUs. For example, as shown in FIG. 10(a), a multiprocessor system includes MPUs 1 and 2 which share a system memory 2. An operating system (OS) for supporting a multiprocessor is also needed to perform multiprocessing. For example, a scheduler in an OS allocates a task or a subdivision of task (thread) to each MPU. As shown in FIG. 11, when the scheduler is started (S100), the scheduler allocates a task to each MPU on the basis of dispatching priorities (S106). The scheduler is started when tasks are synchronized. For example, the scheduler is started by the OS at regular intervals.
The MPUs 1 and 2 shown in FIG. 10(a) comprise cache memories A and B, respectively, which temporarily store a part of data to be stored in the system memory 2. In this specification, “cache memory” will be hereinafter referred simply to as “cache”. In the multiprocessor system, parallel processing is performed while the system memory 2 is shared. Therefore, it is necessary to keep data coherent between memories. In general, the cashes A and B are write-back cashes. Therefore, it is necessary to keep data coherent between the caches A and B.
For example, when the MPUs 1 and 2 request data (DATA_X) stored in the system memory 2, the DATA_X is copied from the system memory 2 to the caches A and B, as shown in FIG. 10(b). When the MPUs 1 and 2 only read data, the same data DATA_X is stored in the caches A and B. Thus data coherency is secured.
However, when the MPU 2 updates the DATA_X stored in the cache B to DATA_Xm, the DATA_X stored in the cache A is no longer the most recent copy of the data but becomes an invalid data which should not be used. In this case, data coherency is not secured. Generally, as shown in FIG. 10(c), the DATA_X in the cache A is invalidated so that the MPU 1 cannot read the invalidated DATA_X.
When the MPU 1 requests reading of DATA_X, the requested DATA_X is not found because the DATA_X has been invalidated in the cache A. Specifically, a cache miss occurs. Since the DATA_X is not found in the cache A, the DATA_Xm stored in the cache B is copied to the cache A, as shown in FIG. 10(d). In this state, the caches A and B store the same data (DATA_Xm), and thus a data coherency is secured. However, when the DATA_Xm is updated in one of the caches A and B, the data stored in the other cache is invalidated and the most recent data stored in the one cache is copied to the other cache in the same manner as described above.
Alternatively, when the MPU 1 requests an updating of data DATA_X with the DATA_X invalidated in the cache A as shown in FIG. 10(c), a cache miss occurs. Since an updated data (DATA_Xm) is not stored in the cache A, the DATA_Xm stored in the cache B is copied to the cache A as shown in FIG. 10(d). After performing optional processes, the DATA_Xm is updated to the DATA_Xm2 (not shown). In this state, the DATA_Xm2 is the most recent copy of the data, and therefore, the DATA_Xm stored in the cache B is invalidated (not shown). A frequent occurrence of data invalidation and cache miss decreases the utilization of the MPU, so that there is no point in using a plurality of MPUs. In this specification, the occurrence of such data invalidation and cache miss will be hereinafter referred to as “ping-pong event”.
Therefore, an object of the present invention is to reduce the occurrence of ping-pong events.